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fujitsu semiconductor data sheet copyright?2010 fujitsu semiconductor limited all rights reserved 2010.8 for the information for microcontroller supports, see the following website. http://edevice.fujitsu .com/micom/en-support/ 8-bit microcontrollers cmos f 2 mc-8fx mb95430h series MB95F432H/f433h/f434h mb95f432k/f433k/f434k description mb95430h is a series of general-purpose, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. note: f 2 mc is the abbreviation of fu jitsu flexible microcontroller. features ?f 2 mc-8fx cpu core instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test branch instructions ? bit manipulation instructions, etc. ? clock ? selectable main clock source main osc clock (up to 16.25 mhz, maximum machine clock frequency: 8.125 mhz) external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) main cr clock (1/8/10/12.5 mhz 2%, maximum machine clock frequency: 12.5 mhz) ? selectable subclock source sub-osc clock (32.768 khz) external clock (32.768 khz) sub-cr clock (typ: 100 khz, min: 50 khz, max: 200 khz) ?timer ? 8/16-bit composite timer 1 channel ? 16-bit ppg 1 channel ? 16-bit free-running timer 1 channel ? 16-bit output compare 2 channels ? time-base timer 1 channel ? watch prescaler 1 channel ? uart/sio 1 channel ? full duplex double buffer ? capable of clock-asynchronous (uart) serial data transfer and clock-synchronous (sio) serial data transfer (continued) ds07?12xxx?1e www.datasheet.in
mb95430h series 2 ds07?12xxx?1e (continued) ?i 2 c 1 channel ? built-in wake-up function ? voltage comparator 4 channels ? operational amplifier (opamp) 1 channel ? software-select programmable gain ? software-select standalone option ? power down function included ? external interrupt 8 channels ? interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ? can be used to wake up the device from different low power consumption (standby) modes ? 8/10-bit a/d converter 17 channels ? 8-bit and 10-bit resolution can be chosen. ? low power consumption (standby) modes ? stop mode ? sleep mode ?watch mode ? time-base timer mode ? i/o port ? MB95F432H/f433h/f434h (maximum no. of i/o ports: 28) general-purpose i/o ports (n-ch open drain) : 1 general-purpose i/o ports (cmos i/o) : 27 ? mb95f432k/f433k/f434k (maximum no. of i/o ports: 29) general-purpose i/o ports (n-ch open drain) : 2 general-purpose i/o ports (cmos i/o) : 27 ? on-chip debug ? 1-wire serial control ? serial writing supported (asynchronous mode) ? hardware/software watchdog timer ? built-in hardware watchdog timer ? built-in software watchdog timer ? low-voltage detection reset circuit ? built-in low-voltage detector ? clock supervisor counter ? built-in clock supervisor counter function ? programmable port input voltage level ? cmos input level / hysteresis input level ? dual operation flash memory ? the erase/write operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. ? flash memory security function ? protects the content of the flash memory www.datasheet.in
mb95430h series ds07?12xxx?1e 3 product line-up (continued) part number parameter MB95F432H mb95f433h mb95f434h mb95f432k mb95f433k mb95f434k type flash memory product clock supervisor counter it supervises the main clock oscillation. program rom capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 240 bytes 496 bytes 240 bytes 240 bytes 496 bytes low-voltage detection reset no yes reset input dedicated selected by software cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8 and 16 bits minimum instruction execution time : 61.5 ns (with machine clock = 16.25 mhz) interrupt processing time : 0.6 s (with machine clock = 16.25 mhz) general- purpose i/o i/o ports (max): 28 cmos i/o: 27 n-ch open drain: 1 i/o ports (max): 29 cmos i/o: 27 n-ch open drain: 2 time-base timer interrupt cycle: 0.256 ms to 8. 3 s (when external clock = 4 mhz) hardware/ software watchdog timer reset generation cycle - main oscillation clock at 10 mhz: 105 ms (min) the sub-cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace three bytes of data. 8/10-bit a/d converter 17 channels (ch. 16 is the channel for opamp output.) 8-bit resolution and 10-bit resolution can be chosen. 8/16-bit composite timer 1 channel the timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel". it has built-in timer function, pwc function, pwm function and input capture function. count clock: it can be selected from internal clocks (seven types) and external clocks. it can output square wave. external interrupt 8 channels interrupt by edge detection (the rising edge, falling ed ge, or both edges can be selected.) it can be used to wake up the device from different standby modes. on-chip debug 1-wire serial control it supports serial writing. (asynchronous mode) uart/sio 1 channel data transfer with uart/sio is enabled. it has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error detection function. it uses the nrz type transfer format. lsb-first data transfer and msb-first data transfer are available to use. clock-asynchronous (uart) serial data tran sfer and clock-synchronous (sio) serial data transfer is enabled. www.datasheet.in
mb95430h series 4 ds07?12xxx?1e (continued) part number parameter MB95F432H mb95f433h mb95f434h mb95f432k mb95f433k mb95f434k i 2 c 1 channel master/slave transmis sion and receiving it has a bus error function, an arbitration function, a transmission direction detection function and a wake-up function. it also has functions of generating and detecting repeated start conditions. 16-bit ppg pwm mode and single-shot mode are available to use. ch. 0 can work with the multi-functional timer or individually. output compare 1 channel of 16-bit free-running timer with a compare buffer 2 channels of 16-bit output compare voltage comparator 4 channels opamp this is an operational amplifier used in an induction heater. it contains 7 software (registers) select close loop gain selections for ground current sensing according to different sense resistor values. the opamp can also work as a standalone opamp. it selects closed loop gain for ground current sensing according to different sense resistor values of a standalone opamp. watch prescaler eight different time intervals can be selected. flash memory it supports automatic programming, embedded algorithm, and write/erase/erase-suspend/ erase-resume commands. it has a flag indicating the completion of the operation of embedded algorithm. number of write/erase cycles: 100000 data retention time: 20 years flash security feature for protecti ng the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package fpt-32p-m30 dip-32p-m06 www.datasheet.in
mb95430h series ds07?12xxx?1e 5 packages and corre sponding products o: available part number package MB95F432H mb95f433h mb95f434h mb95f432k mb95f433k mb95f434k fpt-32p-m30oooooo dip-32p-m06oooooo www.datasheet.in
mb95430h series 6 ds07?12xxx?1e differences among products and notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash erase/write. for details of current consumption, see ? electrical characteristics?. ? package for details of information on each package, see ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage varies, depending on whether the on-chip debug function is used or not. for details of the operating voltage, see ? electrical characteristics?. ? on-chip debug function the on-chip debug function requires that v cc , v ss and one serial wire be connected to an evaluation tool. www.datasheet.in
mb95430h series ds07?12xxx?1e 7 pin assignment v ss pf1/x1 pf0/x0 pf2/r s t p67/cmp 3 _n/an15 p66/cmp 3 _p/an14 p65/cmp 3 _o/uo/ s da p64/cmp2_n/an1 3 p6 3 /cmp2_p/an12 p76/cmp2_o/uck p75/cmp1_n/an11 p74/cmp1_p/an10 pg2/ppg0/x1a/out1 pg1/trg/adtg/x0a/bz/out0 vcc c p60/opamp_p p61/opamp_n p62/opamp_o p12/ec0/ui/ s cl/dbg (top view) lqfp 3 2 fpt- 3 2p-m 3 0 3 2 3 1 3 0 29 2 8 27 26 25 24 2 3 22 21 p7 3 /cmp1_o/out1/ppg p72/cmp0_n/an09 p71/cmp0_p/an0 8 p70/cmp0_o/out0/trg 20 19 1 8 17 1 2 3 4 5 6 7 8 p00/int00/an00 p01/int01/an01/bz p02/int02/an02/uck p0 3 /int0 3 /an0 3 /uo/ s da 9 10 11 12 p04/int04/an04/ui/ s cl p05/int05/an05/to0 p06/int06/an06/to1 1 3 14 15 p07/int07/an07/ec0 16 p67/cmp 3 _n/an15 p66/cmp 3 _p/an14 p65/cmp 3 _o/uo/ s da p64/cmp2_n/an1 3 p6 3 /cmp2_p/an12 p76/cmp2_o/uck p75/cmp1_n/an11 p74/cmp1_p/an10 p7 3 /cmp1_o/out1/ppg p72/cmp0_n/an09 p71/cmp0_p/an0 8 pf0/x0 pf1/x1 v ss pg2/ppg0/x1a/out1 pg1/trg/adtg/x0a/bz/out0 vcc c p60/opamp_p p61/opamp_n p62/opamp_o p12/ec0/ui/ s cl/dbg p00/int00/an00 (top view) s h-dip 3 2 dip- 3 2p-m06 3 2 3 1 3 0 29 2 8 27 26 25 24 2 3 22 21 p70/cmp0_o/out0/trg p07/int07/an07/ec0 p06/int06/an06/to1 p05/int05/an05/to0 20 19 1 8 17 1 2 3 4 5 6 7 8 9 10 11 12 p01/int01/an01/bz p02/int02/an02/uck p0 3 /int0 3 /an0 3 /uo/ s da 1 3 14 15 p04/int04/an04/ui/ s cl 16 pf2/r s t www.datasheet.in
mb95430h series 8 ds07?12xxx?1e pin description (continued) pin no. pin name i/o circuit type* 3 function lqfp32* 1 sh-dip32* 2 15 pg2 c general-purpose i/o port ppg 16-bit ppg output pin x1a subclock i/o oscillation pin out1 output compare ch. 1 output pin 26 pg1 c general-purpose i/o port trg 16-bit ppg trigger input pin adtg a/d converter trigger input pin x0a subclock i/o oscillation pin bz buzzer output pin out0 output compare ch. 0 output pin 37 v cc ? power supply pin 4 8 c ? capacitor connection pin 59 p60 k general-purpose i/o port opamp_p operational amplifier input pin 610 p61 k general-purpose i/o port opamp_n operational amplifier input pin 711 p62 j general-purpose i/o port opamp_o operational amplifier output pin 812 p12 h general-purpose i/o port ec0 8/16-bit composite timer external clock input pin ui uart/sio data input pin scl i 2 c clock i/o pin dbg dbg input pin 913 p00 e general-purpose i/o port int00 external interrupt input pin an00 a/d converter analog input pin 10 14 p01 e general-purpose i/o port int01 external interrupt input pin an01 a/d converter analog input pin bz buzzer output pin 11 15 p02 e general-purpose i/o port int02 external interrupt input pin an02 a/d converter analog input pin uck uart/sio clock i/o pin www.datasheet.in
mb95430h series ds07?12xxx?1e 9 (continued) pin no. pin name i/o circuit type* 3 function lqfp32* 1 sh-dip32* 2 12 16 p03 f general-purpose i/o port int03 external interrupt input pin an03 a/d converter analog input pin uo uart/sio data output pin sda i 2 c data i/o pin 13 17 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin ui uart/sio data input pin scl i 2 c clock i/o pin 14 18 p05 e general-purpose i/o port int05 external interrupt input pin an05 a/d converter analog input pin to0 timer output pin 15 19 p06 e general-purpose i/o port int06 external interrupt input pin an06 a/d converter analog input pin to1 timer output pin 16 20 p07 e general-purpose i/o port int07 external interrupt input pin an07 a/d converter analog input pin ec0 8/16-bit composite timer external clock input pin 17 21 p70 d general-purpose i/o port cmp0_o comparator ch. 0 output pin out0 output compare ch. 0 output pin trg 16-bit ppg trigger input pin 18 22 p71 i general-purpose i/o port cmp0_p comparator ch. 0 positive input pin an08 a/d converter analog input pin 19 23 p72 i general-purpose i/o port cmp0_n comparator ch. 0 negative input pin an09 a/d converter analog input pin 20 24 p73 d general-purpose i/o port cmp1_o comparator ch. 1 output pin out1 output compare ch. 1 output pin ppg 16-bit ppg output pin www.datasheet.in
mb95430h series 10 ds07?12xxx?1e (continued) *1: package code: fpt-32p-m30 *2: package code: dip-32p-m06 *3: for the i/o circuit types, see ? i/o circuit type?. pin no. pin name i/o circuit type* 3 function lqfp32* 1 sh-dip32* 2 21 25 p74 i general-purpose i/o port cmp1_p comparator ch. 1 positive input pin an10 a/d converter analog input pin 22 26 p75 i general-purpose i/o port cmp1_n comparator ch. 1 negative input pin an11 a/d converter analog input pin 23 27 p76 d general-purpose i/o port cmp2_o comparator ch. 2 output pin uck uart/sio clock i/o pin 24 28 p63 i general-purpose i/o port cmp2_p comparator ch. 2 positive input pin an12 a/d converter analog input pin 25 29 p64 i general-purpose i/o port cmp2_n comparator ch. 2 negative input pin an13 a/d converter analog input pin 26 30 p65 l general-purpose i/o port cmp3_o comparator ch. 3 output pin uo uart/sio data output pin sda i 2 c data i/o pin 27 31 p66 i general-purpose i/o port cmp3_p comparator ch. 3 positive input pin an14 a/d converter analog input pin 28 32 p67 i general-purpose i/o port cmp3_n comparator ch. 3 negative input pin an15 a/d converter analog input pin 29 1 pf2 a general-purpose i/o port rst reset pin dedicated reset pin in MB95F432H/f433h/f434h 30 2 pf0 b general-purpose i/o port x0 main clock i/o oscillation pin 31 3 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 32 4 v ss ? power supply pin (gnd) www.datasheet.in
mb95430h series ds07?12xxx?1e 11 i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx.10 m ? cmos output ? hysteresis input ? pull-up control available n-ch re s et output / di g ital output re s et input / hy s tere s i s input s tandby control / port s elect clock input port s elect di g ital output di g ital output s tandby control hy s tere s i s input di g ital output di g ital output s tandby control hy s tere s i s input port s elect x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a s tandby control / port s elect n-ch p-ch port s elect di g ital output di g ital output s tandby control hy s tere s i s input n-ch di g ital output di g ital output di g ital output s tandby control hy s tere s i s input p-ch r pull-up control port s elect p-ch r pull-up control www.datasheet.in
mb95430h series 12 ds07?12xxx?1e (continued) type circuit remarks d ? cmos output ? hysteresis input e ? cmos output ? hysteresis input ? pull-up control available ? analog input f ? cmos output ? hysteresis input ?cmos input ? pull-up control available ? analog input ? n-ch open drain output (as i 2 c output) g ? cmos output ? hysteresis input ? pull-up control available h ? n-ch open drain output ? hysteresis input ?cmos input n-ch p-ch di g ital output di g ital output s tandby control hy s tere s i s input n-ch p-ch p-ch r pull-up control di g ital output di g ital output analo g input a/d control s tandby control hy s tere s i s input n-ch p-ch p-ch r pull-up control i 2 c output control di g ital output di g ital output analo g input a/d control s tandby control hy s tere s i s input cmo s input n-ch p-ch p-ch r pull-up control di g ital output di g ital output s tandby control hy s tere s i s input n-ch s tandby control hy s tere s i s input di g ital output cmo s input www.datasheet.in
mb95430h series ds07?12xxx?1e 13 (continued) type circuit remarks i ? cmos output ? hysteresis input j ? cmos output ? hysteresis input k ? cmos output ? hysteresis input l ? cmos output ? hysteresis input ?cmos input ? n-ch open drain output (as i 2 c output) n-ch p-ch p-ch di g ital output di g ital output analo g input for a/d analo g input for vc analo g input control s tandby control hy s tere s i s input n-ch p-ch p-ch di g ital output di g ital output analo g output analo g output control s tandby control hy s tere s i s input n-ch p-ch p-ch di g ital output di g ital output analo g input analo g input control s tandby control hy s tere s i s input n-ch p-ch p-ch i 2 c output control di g ital output di g ital output s tandby control hy s tere s i s input cmo s input www.datasheet.in
mb95430h series 14 ds07?12xxx?1e notes on device handling ? preventing latch-ups when using the device, ensure that the voltage applied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "1. absolute maximum ratings" of ? electrical charac- teristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. ? stabilizing su pply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluc tuates rapidly even though the fluctuation is within the guaranteed operating range of the v cc power supply voltage. as a rule of voltage stabilizatio n, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscillation stabilizatio n wait time is required fo r power-on reset, wake-up from subclock mode or stop mode. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. always pull up or pull down an unused input pin through a resistor of at least 2 k . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused output pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, prev ent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of approximately 0.1 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. ? dbg pin connect the dbg pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the dbg pin and the v cc or v ss pin when designing the layout of the printed circuit board. the dbg pin should not stay at ?l? level after power-on until the reset output is released. ? rst pin connect the rst pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the rst pin and the v cc or v ss pin when designing the layout of the printed circuit board. the rst /pf2 pin functions as the reset input/output pin after power-on. in addition, the reset output of the rst /pf2 pin can be enabled by the rstoe bit in the sysc1 register, and the rese t input function and the general purpose i/o function can be selected by the rste n bit in the sysc1 register. www.datasheet.in
mb95430h series ds07?12xxx?1e 15 ? c pin use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. c c s dbg r s t ? dbg/rst /c pins connection diagram www.datasheet.in
mb95430h series 16 ds07?12xxx?1e block diagram re s et with lvd fl as h with s ec u rity f u nction (20 k b yte) f 2 mc- 8 fx cpu ram (496 b yte s ) o s cill a tor circ u it cr o s cill a tor clock control on-chip de bu g wild regi s ter extern a l interr u pt comp a r a tor ch. 0 16- b it ppg s top trigger opamp uart/ s io port port pf2 * 1 /r s t * 2 pf1/x1 * 2 pf0/x0 * 2 (pg2/x1a * 2 ) (pg1/x0a * 2 ) (p00/int00 to p07/int07) interr u pt controller b u zzer (p01/bz, pg1/bz) 16- b it free-r u n timer 8 /16- b it compo s ite timer (p05/to0) (p06/to1) p12 * 1 /ec0, (p07/ec0) comp a r a tor ch. 3 p67/cmp 3 _n p66/cmp 3 _p p65/cmp 3 _o comp a r a tor ch. 2 p64/cmp2_n p6 3 /cmp2_p p76/cmp2_o (p02/uck, p76/uck) (p0 3 /uo, p65/uo) (p04/ui, p12 * 1 /ui) 16- b it o u tp u t comp a re (p70/out0, pg1/out0) (p7 3 /out1, pg2/out1) (p12 * 1 /dbg) p72/cmp0_n p71/cmp0_p comp a r a tor ch. 1 p74/cmp1_p p75/cmp1_n i 2 c (p04/ s cl *3 , p12 * 1 / s cl) (p0 3 / s da *3 , p65/ s da *3 ) 8 /10- b it a/d converter p00/an00 p01/an01 p02/an02 p0 3 /an0 3 p04/an04 p05/an05 p06/an06 p70/cmp0_o pg2/ppg, (p7 3 /ppg) pg1/trg, (p70/trg) p60/opamp_p p61/opamp_n p07/an07 (p71/an0 8 ) (p72/an09) (p7 3 /an10) (p74/an11) (p75/an12) (p6 3 /an1 3 ) (p64/an14) (p65/an15) vcc v ss c * 1: * 2: pf2 a nd p12 a re n-ch open dr a in pin s . s oftw a re option *3 : thi s pin will work as a n n-ch open dr a in pin d u ring i 2 c oper a tion. intern a l bus note: pin s in p a renthe s e s indic a te th a t f u nction s of tho s e pin s a re s h a red a mong different re s o u rce s . p62/opamp_o (pg1/atdg) p7 3 /cmp1_o 8 8 2 2 www.datasheet.in
mb95430h series ds07?12xxx?1e 17 cpu core ? memory space the memory space of the mb95430h series is 64 kbyte in size, and consists of an i/o area, a data area, and a program area. the memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. the memory maps of the mb95430h series are shown below. ? memory maps i/o acce ss prohi b ited ram 496 b yte s regi s ter acce ss prohi b ited extended i/o acce ss prohi b ited fl as h 20 k b yte 0000 h 00 8 0 h 0090 h 0100 h 0200 h 02 8 0 h 0f 8 0 h 1000 h b000 h ffff h mb95f4 3 4h/f4 3 4k i/o acce ss prohi b ited ram 240 b yte s regi s ter acce ss prohi b ited acce ss prohi b ited extended i/o acce ss prohi b ited fl as h 8 k b yte 0000 h 00 8 0 h 0090 h 0100 h 01 8 0 h 0f 8 0 h 1000 h b000 h c000 h e000 h ffff h mb95f4 33 h/f4 33 k i/o acce ss prohi b ited ram 240 b yte s regi s ter acce ss prohi b ited extended i/o acce ss prohi b ited acce ss prohi b ited fl as h 4 k b yte fl as h 4 k b yte fl as h 4 k b yte 0000 h 00 8 0 h 0090 h 0100 h 01 8 0 h 0f 8 0 h 1000 h b000 h c000 h f000 h ffff h mb95f4 3 2h/f4 3 2k www.datasheet.in
mb95430h series 18 ds07?12xxx?1e i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ? ? 0007 h sycc system clock control register r/w 0000x011 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r/w xxxxxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock contro l register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ? ? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h pdr7 port 7 data register r/w 00000000 b 0019 h ddr7 port 7 direction register r/w 00000000 b 0020 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 ch. 0 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 ch. 0 r/w 00000000 b 0038 h buzz buzzer control register r/w 00000000 b 0039 h ? (disabled) ? ? www.datasheet.in
mb95430h series ds07?12xxx?1e 19 (continued) address register abbreviation register name r/w initial value 003a h cmr0 voltage comparator control register ch. 0 r/w 000x0001 b 003b h cmr1 voltage comparator control register ch. 1 r/w 000x0001 b 003c h cmr2 voltage comparator control register ch. 2 r/w 000x0001 b 003d h cmr3 voltage comparator control register ch. 3 r/w 000x0001 b 003e h opcr opamp control register r/w 00000011 b 003f h to 0041 h ? (disabled) ? ? 0042 h pcnth0 16-bit ppg status control register upper ch. 0 r/w 00000000 b 0043 h pcntl0 16-bit ppg status control register lower ch. 0 r/w 00000000 b 0044 h ptgs0 16-bit ppg trigger source control register ch. 0 r/w 00000000 b 0045 h ? (disabled) ? ? 0046 h ocuoc 16-bit output compare stop trigger control register r/w 00000000 b 0047 h ? (disabled) ? ? 0048 h eic00 external interrupt circuit control register ch. 0/ch. 1 r/w 00000000 b 0049 h eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h , 004d h ? (disabled) ? ? 004e h sysc2 system control re gister 2 r/w 00000000 b 004f h ? (disabled) ? ? 0050 h ibcr00 i 2 c bus control register 0 r/w 00000000 b 0051 h ibcr10 i 2 c bus control register 1 r/w 00000000 b 0052 h ibsr0 i 2 c bus status register r/w 00000000 b 0053 h iddr0 i 2 c data register r/w 00000000 b 0054 h iaar0 i 2 c address register r/w 00000000 b 0055 h iccr0 i 2 c clock control register r/w 00000000 b 0056 h smc10 uart/sio serial mode control register 1 ch. 0 r/w 00000000 b 0057 h smc20 uart/sio serial mode control register 2 ch. 0 r/w 00100000 b 0058 h ssr0 uart/sio serial status and data register ch. 0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch. 0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch. 0 r 00000000 b 005b h ? (disabled) ? ? 005c h tcdth 16-bit free-running timer data register (upper) r/w 00000000 b 005d h tcdtl 16-bit free-running timer data register (lower) r/w 00000000 b 005e h cpclrh 16-bit free-running timer compare clear register (upper) r 11111111 b 005f h cpclrl 16-bit free-running timer compare clear register (lower) r 11111111 b www.datasheet.in
mb95430h series 20 ds07?12xxx?1e (continued) address register abbreviation register name r/w initial value 0060 h tccsh 16-bit free-running timer control status register (upper) r/w 01000000 b 0061 h tccsl 16-bit free-running timer control status register (lower) r/w 00000000 b 0062 h etccsh 16-bit free-running timer extended control status register (upper) r/w 00000000 b 0063 h etccsl 16-bit free-running timer extended control status register (lower) r/w 00000000 b 0064 h occp0h 16-bit output compare channel 0 register (upper) r 00000000 b 0065 h occp0l 16-bit output compare channel 0 register (lower) r 00000000 b 0066 h occp1h 16-bit output compare channel 1 register (upper) r 00000000 b 0067 h occp1l 16-bit output compare channel 1 register (lower) r 00000000 b 0068 h ocsh 16-bit output compare control status register (upper) r/w 00000000 b 0069 h ocsl 16-bit output compare control status register (lower) r/w 00000000 b 006a h ocmcr 16-bit output compare mode control register r/w 00000000 b 006b h eocs 16-bit output compare extended control status register r/w 00000000 b 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower) r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 0000xxxx b 0075 h ? (disabled) ? ? 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? (disabled) ? ? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h to 0f7f h ? (disabled) ? ? www.datasheet.in
mb95430h series ds07?12xxx?1e 21 (continued) address register abbreviation register name r/w initial value 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b 0f89 h wrarh3 wild register address setting register (upper) ch. 3 r/w 00000000 b 0f8a h wrarl3 wild register address setting register (lower) ch. 3 r/w 00000000 b 0f8b h wrdr3 wild register data setting register ch. 3 r/w 00000000 b 0f8c h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 ch. 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 ch. 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register ch. 0 r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register ch. 0 r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register ch. 0 r/w 00000000 b 0f97 h to 0fa9 h ? (disabled) ? ? 0faa h pdcrh0 16-bit ppg down counter register (upper) ch. 0 r/w 00000000 b 0fab h pdcrl0 16-bit ppg down counter re gister (lower) ch. 0 r/w 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper) ch. 0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower) ch. 0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer register (upper) ch. 0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer register (lower) ch. 0 r/w 11111111 b 0fb0 h to 0fbd h ? (disabled) ? ? 0fbe h pssr0 uart/sio prescaler select register ch. 0 r/w 00000000 b 0fbf h brsr0 uart/sio baud rate setting register ch. 0 r/w 00000000 b 0fc0 h , 0fc1 h ? (disabled) ? ? 0fc2 h aidrh a/d input disable register (upper) r/w 00000000 b 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? www.datasheet.in
mb95430h series 22 ds07?12xxx?1e (continued) ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0fe4 h crth main cr clock trimming register (upper) r/w 0xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 00xxxxxx b 0fe6 h , 0fe7 h ? (disabled) ? ? 0fe8 h sysc1 system configuration register 1 r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r 00000000 b 0feb h wdth watchdog timer selectio n id register (upper) r xxxxxxxx b 0fec h wdtl watchdog timer selectio n id register (lower) r xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of th is bit is indeterminate. www.datasheet.in
mb95430h series ds07?12xxx?1e 23 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 0 irq00 fffa h fffb h l00 [1:0] high low external interrupt ch. 4 external interrupt ch. 1 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 5 external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 uart/sio irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] output compare ch. 0 match irq07 ffec h ffed h l07 [1:0] output compare ch. 1 match irq08 ffea h ffeb h l08 [1:0] ? irq09 ffe8 h ffe9 h l09 [1:0] voltage comparator ch. 0 irq10 ffe6 h ffe7 h l10 [1:0] voltage comparator ch. 1 irq11 ffe4 h ffe5 h l11 [1:0] voltage comparator ch. 2 irq12 ffe2 h ffe3 h l12 [1:0] voltage comparator ch. 3 irq13 ffe0 h ffe1 h l13 [1:0] 16-bit free-running timer (compare match/zero-detect/overflow) irq14 ffde h ffdf h l14 [1:0] 16-bit ppg irq15 ffdc h ffdd h l15 [1:0] i 2 c irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] www.datasheet.in
mb95430h series 24 ds07?12xxx?1e electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6v input voltage* 1 v i v ss ? 0.3 v ss + 6v*2 output voltage* 1 v o v ss ? 0.3 v ss + 6v*2 maximum clamp current i clamp ? 2 + 2 ma applicable to specific pins *3 total maximum clamp current |i clamp | ? 20 ma applicable to specific pins *3 ?l? level maximum output current i ol1 ? 15 ma other than p05 and p06 i ol2 15 p05 and p06 ?l? level average current i olav1 ?4 ma other than p05 and p06 average output current = operating current operating ratio (1 pin) i olav2 ?12 p05 and p06 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ?100ma ?l? level total average output current i olav ?50ma total average output current = operating current operating ratio (total number of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p05 and p06 i oh2 ? ? 15 p05 and p06 ?h? level average current i ohav1 ? ? 4 ma other than p05 and p06 average output current = operating current operating ratio (1 pin) i ohav2 ? ? 8 p05 and p06 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total number of pins) power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c www.datasheet.in
mb95430h series ds07?12xxx?1e 25 (continued) *1: the parameter is based on v ss = 0.0 v. *2: v i and v o must not exceed v cc + 0.3 v. v i must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *3: applicable to the following pins: p00 to p07, p60 to p67, p70 to p76, pf0 and pf1 ? use under recommended operating conditions. ? use with dc volt age (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the hv (high voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcontroller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. hv(high volt a ge) inp u t (0 v to 16 v) protective diode v cc n-ch p-ch r limiting re s i s tor ? input/output equivalent circuit www.datasheet.in
mb95430h series 26 ds07?12xxx?1e 2. recommended operating conditions (v ss = 0.0 v) *1: the value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: this value becomes 2.88 v when the low-voltage detection reset is used. *3: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within thei r recommended operating condition ranges. operation outside these ra nges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4* 1 * 2 5.5* 1 v in normal operation other than on-chip debug mode 2.3 5.5 hold condition in stop mode 2.9 5.5 in normal operation on-chip debug mode 2.3 5.5 hold condition in stop mode smoothing capacitor c s 0.022 1 f *3 operating temperature t a ? 40 + 85 c other than on-chip debug mode + 5 + 35 on-chip debug mode c c s dbg * s ince the dbg pin b ecome s a comm u nic a tion pin in on-chip de bu g mode, s et a p u ll- u p re s i s tor v a l u e su iting the inp u t/o u tp u t s pecific a tion s of p12/ec0/ui/ s cl/dbg. * : r s t ? dbg / rst / c pins connection diagram www.datasheet.in
mb95430h series ds07?12xxx?1e 27 3. dc characteristics (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ *3 max "h" level input voltage v ihi p03, p04, p12, p65 *1 0.7 v cc ?v cc + 0.3 v when cmos input level (hysteresis input) is selected v ihs p00 to p07, p12, p60 to p67, p70 to p76, pf0, pf1, pg1, pg2 *1 0.8 v cc ?v cc + 0.3 v hysteresis input v ihm pf2 ? 0.7 v cc ?v cc + 0.3 v hysteresis input ?l? level input voltage v il p03, p04, p12, p65 *1 v ss ? 0.3 ? 0.3 v cc v when cmos input level (hysteresis input) is selected v ils p00 to p07, p12, p60 to p67, p70 to p76, pf0, pf1, pg1, pg2 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ? 0.3 ? 0.3 v cc v hysteresis input open-drain output application voltage v d p03, p04, p12, p65, pf2 ?v ss ? 0.3 ? v ss + 5.5 v p03, p04 and p65 are open-drain output pins when assigned as the sda/scl pin of i 2 c. ?h? level output voltage v oh1 output pins other than p05, p06, p12 and pf2 i oh = ? 4 ma v cc ? 0.5 ? ? v v oh2 p05, p06 i oh = ? 8 ma v cc ? 0.5 ? ? v ?l? level output voltage v ol1 output pins other than p05 and p06 i ol = 4 ma ? ? 0.4 v v ol2 p05, p06 i ol = 12 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc ? 5? + 5a when pull-up resistance is disabled pull-up resistance r pull p00 to p07, pg1, pg2 v i = 0 v 25 50 100 k when pull-up resistance is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf www.datasheet.in
mb95430h series 28 ds07?12xxx?1e (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ *3 max power supply current* 2 i cc v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?12.122 ma flash memory product (except writing and erasing) ? 39.3 46.8 ma flash memory product (at writing and erasing) ? 13.8 30.3 ma at a/d conversion ? 12.5 23.4 ma when the voltage comparator is operating ? 13.4 22.3 ma when the opamp is operating i ccs v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ? 5.1 13.2 ma i ccl v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = + 25 c ?57168a i ccls v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = + 25 c ? 7.6 92 a i cct v cc = 5.5 v f cl = 32 khz watch mode main stop mode t a = + 25 c ? 4.2 33 a i ccmcr v cc v cc = 5.5 v f crh = 12.5 mhz f mp = 12.5 mhz main cr clock mode ? 9.6 18.2 ma i ccscr v cc = 5.5 v sub-cr clock mode (divided by 2) t a = + 25 c ? 107.4 550 a www.datasheet.in
mb95430h series ds07?12xxx?1e 29 (continued) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: the input levels of p04 can be switched between ?cmos input level? and ?hysteresis input level?. the input level selection register (ilsr) is used to switch between the two input levels. *2: ? the power supply current is determined by the external clock. when the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (i lv d ) to one of the value from i cc to i cch . in addition, when both the low-voltage detection option and the cr osc illator are selected, the power supply current will be the su m of adding up the current consumption of the low-voltage det ection circuit, the current cons umption of the cr oscillators (i crh , i crl ) and a specified value. in on-chi p debug mode, the cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. ? see "4. ac characteristics: (1) clock timing" for f ch and f cl . ? see "4. ac characteristics: (2) source clock/machine clock" for f mp and f mpl . *3: v cc = 5.0 v, t a = 25 c parameter symbol pin name condition value unit remarks min typ *3 max power supply current* 2 i ccts v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz time-base timer mode t a = + 25 c ?0.93.3ma i cch v cc = 5.5 v substop mode t a = + 25 c ? 3.5 24.8 a i lvd v cc current consumption for low-voltage detection circuit only ?26.954 a i crh current consumption for the main cr oscillator ?0.20.6ma i crl current consumption for the sub-cr oscillator oscillating at 100 khz ?64.772 a www.datasheet.in
mb95430h series 30 ds07?12xxx?1e 4. ac characteristics (1) clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: the external clock signal is input to x0 and the inverted external clock signal to x1. parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1: open 1 ? 12 mhz when the main external clock is used x0, x1 * 1 ? 32.5 mhz f crh ?? tbd 12.5 tbd mhz when the main cr clock is used tbd 10 tbd mhz tbd 8 tbd mhz tbd 1 tbd mhz f cl x0a, x1a ? ? 32.768 ? khz when the sub-oscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 200 khz when the sub-cr clock is used clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1: open 83.4 ? 1000 ns when the external clock is used x0, x1 * 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used input clock pulse width t wh1 t wl1 x0 x1: open 33.4 ? ? ns when the external clock is used, the duty ratio should range between 40% and 60%. x0, x1 * 12.4 ? ? ns t wh2 t wl2 x0a ? ? 15.2 ? s input clock rise time and fall time t cr t cf x0 x1: open ? ? 5 ns when the external clock is used x0, x1 * ? ? 5 ns cr oscillation start time t crhwk ? ? ? ? 80 s when the main cr clock is used t crlwk ? ? ? ? 10 s when the sub-cr clock is used www.datasheet.in
mb95430h series ds07?12xxx?1e 31 x0, x1 0. 8 v cc 0.2 v cc 0.2 v cc 0. 8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf when a cry s t a l o s cill a tor or a cer a mic o s cill a tor i s us ed when the extern a l cloc k i s us ed x0 x1 x0 x1 f ch f ch when the extern a l clock i s us ed (x1 i s open) x0 x1 open f ch ? figure of main clock input port external connection x0a 0. 8 v cc 0.2 v cc 0.2 v cc 0. 8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf when a cry s t a l o s cill a tor or a cer a mic o s cill a tor i s us ed when the extern a l cloc k i s us ed x0a x1a x0a x1a open f cl f cl ? figure of subclock input port external connection www.datasheet.in
mb95430h series 32 ds07?12xxx?1e (2) source clock/machine clock (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: this is the clock before it is divided according to the division ratio set by the machine clock divide ratio select bits (sycc:div1 and div0). this source clock is divided to become a machine clock according to the divide ratio set by the machine clock divide ratio select bits (sycc:div1 and div0). in addition, a source clock can be selected fr om the following. ? main clock divided by 2 ? main cr clock ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 80 ? 1000 ns when the main cr clock is used min: f crh = 12.5 mhz max: f crh = 1 mhz ?61?s when the sub-oscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used 1 ? 12.5 mhz when the main cr clock is used f spl ? 16.384 ? khz when the sub-oscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 80 ? 16000 ns when the main cr clock is used min: f sp = 12.5 mhz max: f sp = 1 mhz, divided by 16 61 ? 976.5 s when the sub-oscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.0625 ? 12.5 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the sub- oscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz www.datasheet.in
mb95430h series ds07?12xxx?1e 33 f ch (m a in o s cill a tion) f crh (m a in cr clock) f cl ( sub -o s cill a tion) f crl ( sub -cr clock) s clk ( s o u rce clock) mclk (m a chine clock) m a chine clock divide r a tio s elect b it s ( s ycc:div1, div0) clock mode s elect b it s ( s ycc2: rc s 1, rc s 0) divi s ion circ u it 1 1/4 1/ 8 1/16 divided b y 2 divided b y 2 divided b y 2 ? schematic diagram of the clock generation block oper a ting volt a ge (v) a/d converter oper a tion r a nge 5.5 5.0 4.0 3 .5 3 .0 2.4 16 khz 3 mhz 10 mhz 16.25 mhz s o u rce clock fre qu ency (f s p /f s pl ) oper a ting volt a ge (v) a/d converter oper a tion r a nge 5.5 5.0 4.0 3 .5 3 .0 2.9 16 khz 3 mhz 12.5 mhz 16.25 mhz s o u rce clock fre qu ency (f s p ) ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) mb95430h (without the on-chip debug function) ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) mb95430h (with the on-chip debug function) www.datasheet.in
mb95430h series 34 ds07?12xxx?1e (3) external reset (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: see ?(2) source clock/machine clock? for t mclk . *2: the oscillation time of an oscillator is the time for it to reach 90% of its amplitude. the crystal oscillator has an oscillation time of between seve ral ms and tens of ms. the ceramic oscillator has an oscillation time of between hundreds of s and several ms. the external clock has an oscillation time of 0 ms. the cr oscillator clock has an oscillation time of between several s and several ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns in normal operation oscillation time of the oscillator* 2 + 100 ?s in stop mode, subclock mode, subsleep mode, watch mode, and power-on 100 ? s in time-base timer mode 0.2 v cc r s t 0.2 v cc t r s tl t r s tl 0.2 v cc 0.2 v cc 100 s x0 intern a l oper a ting clock 90 % of a mplit u de o s cill a tion time of o s cill a tor o s cill a tion s t ab iliz a tion w a it time exec u te in s tr u ction intern a l re s et r s t ? in normal operation ? in stop mode, subclock mode, subsleep mode, watch mode and power-on www.datasheet.in
mb95430h series ds07?12xxx?1e 35 (4) power-on reset (v ss = 0.0 v, t a = ? 40 c to + 85 c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. parameter symbol condition value unit remarks min max power supply rising time t r ??50ms power supply cutoff time t off ? 1 ? ms wait time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2. 3 v v ss hold condition in s top mode s et the s lope of ri s ing to a v a l u e b elow 3 0 mv/m s . www.datasheet.in
mb95430h series 36 ds07?12xxx?1e (5) peripheral input timing (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, ec0, adtg, trg 2 t mclk * ?ns peripheral input ?l? pulse width t ihil 2 t mclk * ?ns int00 to int07, ec0, adtg, trg 0. 8 v cc 0. 8 v cc 0.2 v cc 0.2 v cc t ilih t ihil www.datasheet.in
mb95430h series ds07?12xxx?1e 37 (6) uart/sio, serial i/o timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck internal clock operation 4 t mclk *?ns uck uo time t slov uck, uo ? 190 + 190 ns valid ui uck t ivsh uck, ui 2 t mclk *?ns uck valid ui hold time t shix uck, ui 2 t mclk *?ns serial clock ?h? pulse width t shsl uck external clock operation 4 t mclk *?ns serial clock ?l? pulse width t slsh uck 4 t mclk *?ns uck uo time t slov uck, uo ? 190 ns valid ui uck t ivsh uck, ui 2 t mclk *?ns uck valid ui hold time t shix uck, ui 2 t mclk *?ns 0. 8 v0. 8 v 2.4 v t s lov t iv s h t s hix 2.4 v 0. 8 v uck uc ui 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc t s cyc ? internal shift clock mode t s lov t iv s h t s hix 2.4 v 0. 8 v uck uc ui 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc t s l s h t s h s l ? external shift clock mode www.datasheet.in
mb95430h series 38 ds07?12xxx?1e (7) low-voltage detection (v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max release voltage v dl+ 2.52 2.7 2.88 v at power supply rise detection voltage v dl- 2.42 2.6 2.78 v at power supply fall hysteresis width v hys 70 100 ? mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 3000 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 300 ? ? s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ??300s reset detection delay time t d2 ? ? 20 s v hy s t d2 t d1 t r t f v cc v on v off v dl+ v dl- time time intern a l re s et s ign a l www.datasheet.in
mb95430h series ds07?12xxx?1e 39 (8) i 2 c timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: the maximum t hd;dat in the standard-mode is applicable only when the time during which the device is holding the scl signal at ?l? (t low ) does not extend. *3: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, provided that the condition of t su;dat 250ns is fulfilled. (continued) parameter symbol pin name condition value unit standard- mode fast-mode minmaxminmax scl clock frequency f scl scl r = 1.7 k , c = 50 pf *1 01000400khz (repeated) start condition hold time sda scl t hd;sta scl, sda 4.0 ? 0.6 ? s scl clock ?l? width t low scl 4.7 ? 1.3 ? s scl clock ?h? width t high scl 4.0 ? 0.6 ? s (repeated) start condition hold time scl sda t su;sta scl, sda 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl, sda 0 3.45 *2 00.9 *3 s data setup time sda scl t su;dat scl, sda 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl, sda 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl, sda 4.7 ? 1.3 ? s s da s cl t wakeup t hd; s ta t s u;dat f s cl t hd; s ta t s u; s ta t low t hd;dat t high t s u; s to t buf www.datasheet.in
mb95430h series 40 ds07?12xxx?1e (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k , c = 50 pf* 1 (2 + nm/2)t mclk ? 20 ? ns master mode scl clock ?h? width t high scl (nm/2)t mclk ? 20 (nm/2)t mclk + 20 ns master mode start condition hold time t hd;sta scl, sda ( ? 1 + nm/2)t mclk ? 20 ( ? 1 + nm)t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl, sda (1 + nm/2)t mclk ? 20 (1 + nm/2)t mclk + 20 ns master mode start condition setup time t su;sta scl, sda (1 + nm/2)t mclk ? 20 (1 + nm/2)t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl, sda (2 nm + 4)t mclk ? 20 ?ns data hold time t hd;dat scl, sda 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl, sda ( ? 2 + nm/2)t mclk ? 20 ( ? 1 + nm/2)t mclk + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing inter- rupt and scl rising t su;int scl (nm/2)t mclk ? 20 (1 + nm/2)t mclk + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to the interrupt at the 8th scl . www.datasheet.in
mb95430h series ds07?12xxx?1e 41 (continued) (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: ? see ?(2) source clock/machine clock? for t mclk . ? m represents the cs4 bit and cs3 bit (bit 4 and bit 3) in the i 2 c clock control register (iccr0). ? n represents the cs2 bit to cs0 bit (bit 2 to bit 0) in the i 2 c clock control register (iccr0). ? the actual timing of i 2 c is determined by the values of m and n set by the machine clock (t mclk ) and the cs4 to cs0 bits in the iccr0 register. ? standard-mode: m and n can be set to values in the following range: 0.9 mhz < t mclk (machine clock) < 10 mhz. the usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < t mclk 10 mhz ? fast-mode: m and n can be set to values in the following range: 3.3 mhz < t mclk (machine clock) < 10 mhz. the usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22), (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < t mclk 10 mhz parameter sym- bol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k , c = 50 pf* 1 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl, sda 2 t mclk ? 20 ?ns undetected when 1 t mclk is used at reception stop condition detection t su;sto scl, sda 2 t mclk ? 20 ?ns undetected when 1 t mclk is used at reception restart condition detection condition t su;sta scl, sda 2 t mclk ? 20 ?ns undetected when 1 t mclk is used at reception bus free time t buf scl, sda 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl, sda 2 t mclk ? 20 ?ns at slave transmission mode data setup time t su;dat scl, sda t low ? 3 t mclk ? 20 ?ns at slave transmission mode data hold time t hd;dat scl, sda 0 ? ns at reception data setup time t su;dat scl, sda t mclk ? 20 ? ns at reception sda scl (at wakeup function) t wakeup scl, sda oscillation stabilization wait time + 2 t mclk ? 20 ?ns www.datasheet.in
mb95430h series 42 ds07?12xxx?1e (9) voltage compare timing (v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter pin name value unit remarks min typ max voltage range cmpn_p, cmpn_n (n = 0,1,2,3) 0?v cc ? 1.3 v offset voltage cmpn_p, cmpn_n (n = 0,1,2,3) ? 10 ? + 10 mv delay time cmpn_o (n = 0,1,2,3) ? 650 1210 ns 5 mv overdrive ? 140 420 ns 50 mv overdrive power down delay cmpn_o (n = 0,1,2,3) ? ? 1210 ns power down recovery pd: 1 0 0??ns power down effective pd: 0 1 output: ?h? level power up stabilization time cmpn_o (n = 0,1,2,3) ? ? 1210 ns output stabilization time at power up www.datasheet.in
mb95430h series ds07?12xxx?1e 43 (9) operational amplifier timing ? open loop configuration (v cc = 4.0 v to 5.5 v, t a = ? 40 c to + 85 c) parameter pin name value unit remarks min typ max input voltage range opamp_p, opamp_n 0.1 ? 1.5 v output voltage range opamp_o 0.1 ? v cc ? 0.1 v output resistor load opamp_o 220k ? ? ohm minimum driving resistor value output capacitor load opamp_o ? ? 20 pf ad loading (maximum esr = 10k) offset voltage opamp_o ? ? 10 mv open loop bandwidth opamp_o 3 ? ? mhz open loop gain opamp_o 75 85 ? db ad loading common mode rejection rati o opamp_o 60 ? ? db ad loading power supply rejectio n ratio opamp_o 65 ? ? db power down recovery time opamp_o ? ? 200 s slew rate opamp_o 0.3 ? ? v/s large signal response opamp_o ? ? 6 s small signal response opamp_o ? ? 500 ns output stabiliz ation time opamp_o ? ? 60 s after changes in values of res0-res2 www.datasheet.in
mb95430h series 44 ds07?12xxx?1e ? closed loop configuration (v cc = 4.0 v to 5.5 v, t a = ? 40 c to + 85 c) *: gain error = 1 ? (actual gain / design gain) parameter pin name value unit remarks min typ max minimum input voltage range (10x, 20x, 60x) opamp_p, opamp_n ? 0.07 0.09 v minimum input voltage range (30x, 40x, 50x) opamp_p, opamp_n ? 0.07 0.10 v maximum input voltage range (10x, 20x, 30x, 40x, 50x, 60x) opamp_p, opamp_n ??v cc /gain v output voltage range opamp_o 0.1 ? v cc ? 0.1 v output capacitor load opamp_o ? ? 20 pf ad loading (maximum esr = 10k) closed loop bandwidth o pamp_o 1 ? ? mhz ad loading closed loop gain opamp_o 10 ? 60 v/v selectable closed loop gain error* (10x, 20x, 30x, 40x, 50x) opamp_o ? ? 10% ? closed loop gain error* (60x) opamp_o ? ? 15% ? power down recovery time opamp_o ? ? 200 s slew rate opamp_o 0.3 ? ? v/s large signal response opamp_o ? ? 6 s small signal response opamp_o ? ? 500 ns output stabiliz ation time opamp_o ? ? 60 s after changes in values of res0-res2 www.datasheet.in
mb95430h series ds07?12xxx?1e 45 5. a/d converter (1) a/d converter electrical characteristics (v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ??10bit total error ? 3? + 3lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot v ss ? 1.5 lsb v ss + 0.5 lsb v ss + 2.5 lsb v full-scale transition voltage v fst v cc ? 4.5 lsb v cc ? 2 lsb v cc + 0.5 lsb v compare time ? 0.9 ? 16500 s 4.5 v v cc 5.5 v 1.8 ? 16500 s 4.0 v v cc < 4.5 v sampling time ? 0.6 ? s 4.5 v v cc 5.5 v, with external impedance < 5.4 k 1.2 ? s 4.0 v v cc < 4.5 v, with external impedance < 2.4 k analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain v ss ?v cc v www.datasheet.in
mb95430h series 46 ds07?12xxx?1e (2) notes on using the a/d converter ? external impedance of analog input and its sampling time ? the a/d converter has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. in addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. ? a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. note: the v a l u e s a re reference v a l u e s . 4.5 v v cc 5.5 v 4.0 v v cc < 4.5 v 1.95 k (m a x) 8 .9 8 k (m a x) 17 pf (m a x) v cc r c 17 pf (m a x) comp a r a tor an a log inp u t d u ring sa mpling: on r c ? analog input equivalent circuit [extern a l imped a nce = 0 k to 100 k ] extern a l imped a nce [k ] extern a l imped a nce [k ] minim u m sa mpling time [ s ] minim u m sa mpling time [ s ] [extern a l imped a nce = 0 k to 20 k ] 100 90 8 0 70 60 50 40 3 0 20 10 0 20 1 8 16 14 12 10 8 6 4 2 0 0246 8 10 12 14 1 02 3 4 (v cc 4.5 v) (v cc 4.0 v) (v cc 4.5 v) (v cc 4.0 v) ? relationship between external impedance and minimum sampling time www.datasheet.in
mb95430h series ds07?12xxx?1e 47 (3) definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device to the full-scale transition point (?11 1111 1111? ?11 1111 1110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a theoretical value. the error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v f s t ide a l i/o ch a r a cteri s tic s 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h digit a l o u tp u t digit a l o u tp u t 2 l s b v ot 1 l s b 0.5 l s b tot a l error an a log inp u t an a log inp u t 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h act ua l conver s ion ch a r a cteri s tic ide a l ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic n v nt : a/d converter digit a l o u tp u t v a l u e : volt a ge a t which the digit a l o u tp u t tr a n s it s from (n - 1) h to n h {1 l s b (n-1) + 0.5 l s b} v nt tot a l error of digit a l o u tp u t n v nt - {1 l s b (n - 1) + 0.5 l s b} 1 l s b [l s b] = v cc - v ss 1024 (v) 1 l s b = v ss v cc v ss v cc www.datasheet.in
mb95430h series 48 ds07?12xxx?1e (continued) zero tr a n s ition error line a rity error f u ll- s c a le tr a n s ition error 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h digit a l o u tp u t differenti a l line a r error of digit a l o u tp u t n v (n+1)t - v nt 1 l s b - 1 = line a rity error of digit a l o u tp u t n v nt - {1 l s b n + v ot } 1 l s b = digit a l o u tp u t an a log inp u t 001 h 002 h 3 fc h 3 fd h 00 3 h 3 fe h 3 ff h 004 h act ua l conver s ion ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic v ot (me asu rement v a l u e) act ua l conver s ion ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic v f s t (me asu rement v a l u e) v ss v cc v ss v cc v ss v cc v ss v cc an a log inp u t digit a l o u tp u t an a log inp u t ide a l ch a r a cteri s tic {1 l s b n + v ot } act ua l conver s ion ch a r a cteri s tic ide a l ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic v ot (me asu rement v a l u e) v f s t (me asu rement v a l u e) v nt differenti a l line a rity error (n-2) h (n-1) h n h (n+1) h digit a l o u tp u t an a log inp u t act ua l conver s ion ch a r a cteri s tic ide a l ch a r a cteri s tic v nt act ua l conver s ion ch a r a cteri s tic v (n+1)t n v nt : a/d converter digit a l o u tp u t v a l u e : volt a ge a t which the digit a l o u tp u t tr a n s it s from (n - 1) h to n h v ot (ide a l v a l u e) = v ss + 0.5 l s b [v] v f s t (ide a l v a l u e) = v cc - 2 l s b [v] ide a l ch a r a cteri s tic www.datasheet.in
mb95430h series ds07?12xxx?1e 49 6. flash memory write/erase characteristics *1: t a = + 25 c, v cc = 5.0 v, 100000 cycles *2: t a = + 85 c, v cc = 3.0 v, 100000 cycles *3: this value is converted from the result of a techno logy reliability assessment. (t he value is converted from the result of a high temperature accelerated test using the arrhenius equation with the average temperature being + 85 c). parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.2* 1 0.5* 2 s the time of writing 00 h prior to erasure is excluded. sector erase time (16 kbyte sector) ?0.5* 1 7.5* 2 s the time of writing 00 h prior to erasure is excluded. byte writing time ? 21 6100* 2 s system-level overhead is excluded. erase/write cycle 100000 ? ? cycle power supply voltage at erase/ write 3.0 ? 5.5 v flash memory data retention time 20* 3 ? ? year average t a = + 85 c www.datasheet.in
mb95430h series 50 ds07?12xxx?1e mask options no. part number MB95F432H mb95f433h mb95f434h mb95f432k mb95f433k mb95f434k selectable/fixed fixed 1 low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset with dedicated reset input without dedicated reset input www.datasheet.in
mb95430h series ds07?12xxx?1e 51 ordering information part number package MB95F432Hpmc-g-sne2 mb95f432kpmc-g-sne2 mb95f433hpmc-g-sne2 mb95f433kpmc-g-sne2 mb95f434hpmc-g-sne2 mb95f434kpmc-g-sne2 32-pin plastic lqfp (fpt-32p-m30) MB95F432Hp-g-sh-sne2 mb95f432kp-g-sh-sne2 mb95f433hp-g-sh-sne2 mb95f433kp-g-sh-sne2 mb95f434hp-g-sh-sne2 mb95f434kp-g-sh-sne2 32-pin plastic sh-dip (dip-32p-m06) www.datasheet.in
mb95430h series 52 ds07?12xxx?1e package dimension please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 32-pin plastic lqfp lead pitch 0.80 mm package width package length 7.00 mm 7.00 mm lead shape gullwing sealing method plastic mold mounting height 1.60 mm max 32-pin plastic lqfp (fpt-32p-m30) (fpt-32p-m30) c 7.000.10(.276.004)sq 0.80(.031) "a" 0.10(.004) 9.000.20(.354.008)sq 18 17 24 9 16 25 32 index 0~7 0.600.15 (.024.006) 0.25(.010) 0.100.05 (.004.002) details of "a" part 0.10(.004) * 2009-2010 fujitsu semiconductor limited f32051s-c-1-2 0.20(.008) m 0.35 +0.08 ? 0.03 +.003 ? .001 .014 0.13 +0.05 ? 0.00 +.002 ? .000 .005 (.063) max 1.60 max (mounting height) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. www.datasheet.in
mb95430h series ds07?12xxx?1e 53 (continued) please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 3 2-pin pl as tic s dip le a d pitch 1.77 8 mm low s p a ce 10.16 mm s e a ling method pl as tic mold 3 2-pin pl as tic s dip (dip- 3 2p-m06) (dip- 3 2p-m06) c 200 3 -2010 fujit s u s emiconductor limited d 3 201 8s -c-1- 3 (. 3 50 .010) *8 . 8 9 0.25 1.77 8 (.070) 1.27(.050) 10.16(.400) index * 2 8 .00 1.102 +0.20 ? 0. 3 0 ? .012 +.00 8 4.70 .1 8 5 +0.70 ? 0.20 ? .00 8 +.02 8 3 . 3 0 .1 3 0 +0.20 ? 0. 3 0 ? .012 +.00 8 max. 1.02 .040 ? 0.20 ? .00 8 +.012 +0. 3 0 min. 0.51(.020) 0~15 m 0.25(.010) .019 0.4 8 +0.0 8 +.00 3 ? .005 ? 0.12 0.27 .011 ? .00 3 ? 0.07 +.001 +0.0 3 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . www.datasheet.in
mb95430h series 54 ds07?12xxx?1e memo www.datasheet.in
mb95430h series ds07?12xxx?1e 55 memo www.datasheet.in
mb95430h series fujitsu semiconductor limited nomura fudosan shin-yokohama bldg. 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/se rvices/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further inform ation please cont act each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docu ment are presented solely for t he purpose of reference to show examples of op erations and uses of fuji tsu semiconductor device; fujitsu semiconductor does not warrant proper operation of th e device with respect to use based on such information. when you develop equipment incorporat ing the device based on such inform ation, you must assume any res ponsibility arising out of su ch use of the information. fujitsu semicond uctor assumes no liability for any damages whatsoev er arising out of the use of the information. any information in this document, including descriptions of func tion and schematic diagrams, sha ll not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyrig ht, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconduc tor assumes no liability for any infringe ment of the intellec tual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household us e, but are not designed, developed and m anufactured as contemplated (1) for use accomp anying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requirin g extremely high reliability (i.e., submer sible repeater and artificial satellite). please note that fujits u semiconductor will not be liable ag ainst you and/or any third party for any claims or damages aris- ing in connection with above-m entioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety de sign measures into your facility a nd equipment such as redundancy, fire protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade contro l law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department www.datasheet.in

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